Hardly there is any product that can sell this well before it has even been listed. Owing to the overwhelmingly positive reviews, Holo Audio May did just that.
Holo Audio has made superbly excellent products that their DACs have garnered over thousands of fave and positive reviews from owners and reviewers worldwide. They are now synonymous with the level of high end and high performance with every ounce of value their products are worth.
This has definitely been an exciting progress for the business of QA to secure the dealership for Holo Audio in Singapore and regions, at the same time furnishing the customers here another excellent choice of options in DACs, especially when R2R is concerned.
Essentially the May DAC of Holo Audio is the flagship of the lineup and it does not really need much introduction because it is such a famed model of DAC. The product listing is here for order with the primary information together with links to some of the major review links attached. What comes below are really more of the technical stuffs of May, especially the L3/KTE, where Holo Audio tries to provide a detailed breakdown of the May’s capabilities.
The May is a DUAL mono DAC. so there is a dedicated DAC Module for each left and right channel. Each channel is individually powered by it’s dedicated O-type FLATWIRE transformer found in all three models. We have found after careful testing this new transformer type outperforms ALL transformers we have ever tested to this date. Near zero leakage, improved dynamics and overall spectacular performance. They are handmade for this DAC specifically and deliver world-class performance you would expect.
May DAC also has a new screen on the front that appears the same as the Spring 2 on initial glance. Font size is bigger than Spring 2 but smaller than Spring 1. CD track-time information is displayed when using S/PDIF inputs! This is done by extracting additional data from SPDIF. This a part of CD red book standard but nobody notices this and often forgets this cool feature or doesn’t know how to extract the data! This will lead a fashion for other DAC developer to support this feature. Customers will surely love this subtle feature. The screen is much better contrast and viewing angles and one of the first things one may notice.
The May also has a front power button now! It’s been a request by many customers and gone are the days of a good old reach around to get the DAC to be turned on. As mentioned before above, the DAC has a soft start circuit. So it takes a moment for it to charge up and pull power without blowing the fuse. It actually uses the same exact value of fuse that our Spring 1 and Spring 2 has but with two transformers in this implementation. Without this soft start, one being a blown fuse can occur from power surge, and there could also be pop noises happening. No chance of these things to happen now as we have carefully designed the circuit to be a zero-compromise design.
DAC “May” is the design of a new generation, it’s HoloAudio’s finest technology all designed by Jeff Zhu, the engineer behind these great products. It’s a full discrete R2R type of audio decoder and does not have off the shelf-DAC chip! This is a bespoke custom-designed core DUAL MONO DAC modules that are truly a breakthrough with technology for any DAC chip today. The May is here to achieve new heights, new dynamics and simply a full spectrum of audio to please the aural senses.
May DAC was carefully implemented with some of the finest components.
More about the May DAC
- The new generation of linear compensation technology solves the accuracy errors caused by resistor tolerance, after compensation, reaching a variance of 0.00005% tolerance accuracy.
- Proprietary anti-jitter technology that provides a full amplitude of anti-jitter without increasing noise floor and other undesirable effects.
- Based on this new generation of technology May “梅” can provide a SINAD of >115dB and a dynamic range of >130dB, which represents the performance limit reached by today’s most advanced R2R architecture DAC.
- Using the ultimate performance of PLL+FIFO technology, provides 0.1Hz Third-Order low-pass ability to inhibit jitter. It also uses a high-performance femtosecond VCXO as the PLL clock source. Under the premise of being almost immune to the front-end jitter, it can also lock up to 1.5us-2us @ 1KHz signal with high jitter. (It can lock up to 1.5us-2us @ 1kHz signal with high jitter on the premise of almost being immune to front-end jitter).
- Dual Mono DAC L/R channels are independently powered by their own dedicated transformer in the PSU chassis. This provides better channel separation and more accurate sound stage.
- Official Support USB and I2S up to DSD1024 and PCM1.536MHz sample rate.
- The USB interface uses proprietary firmware with ultra-low latency, a highly reliable data transmission, ideal USB eye pattern measurements that contributes to 2-4 times higher performance than official firmware.
- Two sets of independent HDMI-I2S input interfaces are provided, and each set of I2S has a four-way independent circuit, as opposed to standard LVDS chip, making I2S clock signals subject to lower interference and lower jitter. In addition, each group of I2S inputs can be configured with specific pinout configuration, making it compatible with most of the HDMI-I2S digital devices on the market.
Technical information about May custom PLL circuit
Now the May is implemented with femto clocks, and also new discrete ultra high performance voltage regulators. It has an advanced PLL (phase lock loop) circuit that is completely custom built for ultra high performance anti jitter performance. Even the highest levels of jitter are near eliminated which delivers world class performance. Using Crystek VXCO clocks that will take any incoming digital signal and reclock it to perfection! This feature can be enabled or disabled to test and prove it’s performance is truly spectacular. Note: this is NOT an off the shelf PLL, but it’s truly the most powerful PLL found in a DAC. Or at least to our knowledge it’s the most powerful PLL ever. S/PDIF usually is a not a good protocol because it’s very old and dated! It was designed in 70s together with CD with Sony and Philips. As you may know, It encodes the data signal together with clock signal so it can be transferred by a one-core cable. It makes the cable easy to source, but to encode the data to clock at the transmit side and decode the clock from data at the receiving side, creates jitter. Toslink is a fiber glass version of S/PDIF. So Toslink adds even more jitter while doing electronic to photon and photon to electronic translation. So people will see clearly that I2S is usually better than S/PDIF because I2S has 4 separate signal, 3 clocks 1 data. So it does not have encoding-decoding stuff and thus having a better jitter performance. This is important to know.
A common technique to improve the clock signal from SPDIF is PLL. A PLL is to use a local clock generator to track the source clock. You know jitter is actually a time deviation problem. For example, the first period frequency is 44101Hz and the following second period is 44099Hz. Thus it has 2/44100 jitter. A PLL is to smooth the time deviation of clock. So after the PLL, it can be 44100.9-44099.1(this is a weak/poor performing PLL). Or it can be 44100.1 – 44099.9 (this is a strong performance PLL). Usually, a S/PDIF chip, like AK4118A, has an internal PLL. AK4118A is good chip compared to other S/PDIF receiver chip and it marks 50ps jitter. It’s the best we can get from a commercial chip. But it’s far from ideal, and definitely not enough for a HiFi standard we are implementing in the May DAC. So we need a significantly stronger performing PLL. If the PLL is strong enough, it can smooth the 44101-44009 source clock to 44100.00001-44009.99999(very close to ideal 44100-44100)
But to make a stronger PLL is not easy, it’s actually incredibly difficult. First you need a powerful local clock source. A fixed clock can’t be used because it need to be adjusted to follow source clock rate. A common solution to use a VCO (voltage controlled oscillator). VCO is made by resistors, capacitors and inductors. The cost is low but performance is not so great. So, a better solution is to use VCXO(Voltage controlled crystal oscillator), it uses crystal as oscillator and crystal is a far better oscillator. The VCXO we used in May is Crystek’s CVHD-957. This the best VCXO we can get now.
The second hard problem is, the data need to be synchronized with clock. For example, the source has 44101-44099 clock from S/PDIF and that also means it has 44101 samples in first period and 44099 samples in second period. So a good local 44100-44100 clock will have to throw away one sample in first period and lack one sample in second period. An easy fix to it is to use digital filter to smooth the data and it calls ASRC, but ASRC actually modified the data. So after ASRC, the data is modified thus not bit perfect anymore. And digital filter can also generate time domain problems like ringing artifacts. So, a digital filter is not a good way to solve this problem, or you can say, it solves a problem by introducing another problem.
May uses a fifo buffer to store the extra one sample in first period and release it in second period. So it has no harm to data. The difficulty for this design is how to manage fifo buffer. It can be a problem when you have a long-term jitter. And long-term jitter is actually called low frequency phase noise in a frequency domain point of view. To explain it easily, let’s take a example, a long term jitter can be like this, 44101-44102-44103-44104-44105-44104-44103-44102-44101-44100-44099-44098-44097-44096-44095-44096-44097-44098-44099-44100. So you see, it will have 25 extra samples in first ten periods, so the fifo buffer need to able store enough of them and release it in next 10 periods.
So, as a result, May’s PLL’s corner frequency is set to 0.05-0.1Hz in 3-orders. Than means it can reduce a 10s long term jitter by 90%, 1s period jitter by 99%, 0.1s period jitter by 99.9%. That maybe the most powerful PLL in this industry. And the most important is, it won’t lose data, it can still lock the source while huge jitter comes in. When you compared other similar PLL in the industry, you can see it simply unlocks the signal when huge jitter comes in. So, in that way, it simply stops you from listening, it tells you there is a problem but does not solve it. Compared to other competitors PLL. They won’t remove the jitter so clean, and simply unlock the signal for more than 10ns jitters.
May’s input and output interface:
- Digital input interface includes
- Enhanced USB (ground isolation) + Titanis 2.0 circuit + KYCON industrial High retention USB Connector (improved impedance spec) – Proprietary inhouse firmware w/ ultra low latency performance. Ultra low noise voltage regulation
- RCA coaxial
- BNC coaxial
- optical fiber/Toslink
- I2S (HDMI) – improved ultra high performance 4way custom circuit (NOT traditional LVDS chip anymore) backwards compatible
- I2S-2 (HDMI) – improved ultra high performance 4way custom circuit (NOT traditional LVDS chip anymore) backwards compatible
- All digital input interface supports DSD (DOP mode).
- Analog Output interface: single-ended, balanced.
May DAC R2R structure and design + Input/output Stage
Modern and popular delta-sigma type DAC differs from R2R within one clock analog value can recover a sampling point, and the delta-sigma is used to represent an analog signal after passing through oversampling and high-speed digital switching 0 and 1. In comparison, the conversion structure of R2R is most direct and pure, but delta-sigma is essentially a digital chip, high-speed digital signals 0 and 1 switch to the low-pass filter to process the analog signal and this process is prone to various problems, produce digital sound (digititus) and also in the super-sampling process will inevitably cause some ringing and distortion. But DAC R2R structure requires high-precision resistor network which the cost can be very expensive. And the digital delta-sigma DAC chip in comparison is very low cost.
Patented R2R technology.
This is the first discrete DAC that has Linear compensation and this allows for ultimate music reproduction accuracy. Dual R2R ladder network with advanced architecture for PCM, and Dual Resistor Ladder network with optimized architecture for DSD!
I/O stages: There is an Op Amp used for input stage and discrete component used for the output stage. The discrete output stage is working in pure class A. It’s BiPolar Junction Transistors, direct coupled.
A common question we get…” Why do you use an Op amp at the input of the DAC?”
The input stage with an opamp is a good choice. It has a paired transistor input by the nature it is manufactured. But an opamp for the output stage is limited due to it’s size and the thermal capability. Also, no one will offer an opamp with class A output as it’s efficiency is so low. So an opamp used as input and discrete output combined together will have an advantage. It doesn’t mean that all discrete is not good. Actually, if we need to achieve enough low distortion. It needs at least 30-40 transistors. Which not only will it be huge and waste of space but it will also be too costly. To beat the opamp’s performance, a simple discrete architecture is not possible, although an all-discrete design looks beautiful.
We use opamp+discrete architecture for the amp parts of May. Opamp is used for the input stage, discrete is used for the output stage. All the transistors in the opamp are in the same die, then it is matched by nature. This is key because by now, there are few choice for low noise matched pair transistors but an opamp has plenty of them inside. The Output stage is discrete because it generates a bit of heat. We need a class A output stage. So you can see May is very hot compared to other DACs. An opamp output simply can’t handle that power.
The true balanced DUAL MONO circuit design
XLR is using all of the circuit and RCA is just using half of them. The balanced output has better performance (THD, noise) and also better common mode rejection rate. If you’re listening environment contains interference, either from AC power or from EMI/RF then you will find a full balanced system can really help significantly.
With diverse and flexible sampling mode conversion mode
1: NOS mode: has no digital oversampling, the raw data is directly converted to analog. Because digital oversampling will produce time-domain distortions, such as ringing, NOS avoids these problems.
2: OS mode: PCM is over sampled to PCM at a higher frequency, DSD is over sampled to DSD at a higher frequency, and then digital is converted to analog.
3: OS PCM mode: in either PCM or DSD the data will be oversampled to PCM and then digital is converted to analog.
4: OS DSD mode: in either PCM or DSD the data will be oversampled to DSD and then digital is converted to analog.